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general description the DS3930 contains six 256-position nonvolatile (nv) potentiometers, 64 bytes of nv user eeprom memory, and four programmable nv i/o pins. the six poten- tiometers all share a common low side. the potentiome- ters are separated into two groups of three 50k ? potentiometers in parallel. each group of three poten- tiometers shares a common high side and forms an equivalent resistance of 16.6k ? (three 50k ? poten- tiometers in parallel). applications rf transceivers voltage references power supply calibration mobile phones and pdas fiber optic transceiver modules portable electronics radio tuners small, low-cost replacement for mechanical potentiometers features ? six 256-position nv potentiometers ? four general-purpose nv i/o pins ? 64 bytes of user eeprom memory ? 0 to 5.5v on any potentiometer terminal, independent of v cc ? all six potentiometers share a common low side ? potentiometers separated into two groups of three potentiometers, each sharing a common high side ? 2-wire serial interface ? wide supply range (2.7v to 5.5v) ? up to eight DS3930s can share the same 2-wire bus DS3930 hex nonvolatile potentiometer with i/o and memory _____________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 hi 0-2 w 0 w 1 w 2 sda a2 a1 a0 top view lo 0-5 hi 3-5 w 3 w 4 i/o 2 i/o 1 i/o 0 scl 12 11 9 10 w 5 i/o 3 gnd v cc tssop DS3930 pin configuration a2 sda gnd scl i/o 3 i/o 2 i/o 1 i/o 0 lo 0-5 a0 a1 hi 0-2 hi 3-5 w 0 w 1 w 2 w 3 w 4 w 5 v cc v cc v cc v cc decoupling cap 0.1 f 2-wire interface 4.7k ? 4.7k ? digital nonvolatile i/o digital nonvolatile i/o wiper terminals wiper terminals DS3930 t ypical operating circuit ordering information rev 0; 4/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part pin-package DS3930 e 20 tssop
DS3930 hex nonvolatile potentiometer with i/o and memory 2 ______________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40 to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc relative to ground...................... -0.5v to +6.0v voltage on i/o 0 , i/o 1 , i/o 2 , i/o 3 , sda, scl, a0, a1, and a2 relative to ground* .............................. -0.5v to (v cc + 0.5v) voltage on lo 0-5 , w 0-5 , hi 0-2 , and hi 3-5 relative to ground ............................................-0.5v to +6.0v current through w 0-5 ........................................................ ?ma operating temperature range .......................... -40? to +85? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature.................. see ipc/jedec j-std-020a parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.7 +5.5 v input logic 1 (sda, scl, a0, a1, a2, i/o 0 , i/o 1 , i/o 2 , i/o 3 ) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a0, a1, a2, i/o 0 , i/o 1 , i/o 2 , i/o 3 ) v il -0.3 0.3 x v cc v wiper current i w -1 +1 ma potentiometer terminals (lo 0-5 , w 0-5 , hi 0-2 , and hi 3-5) v cc = +2.7v to +5.5v -0.3 +5.5 v dc electrical characteristics (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise specified.) parameter symbol conditions min typ max units input leakage i il -1 +1 ? v ol1 3ma sink current 0 0.4 v low-level output voltage (sda, i/o 0 , i/o 1 , i/o 2 , i/o 3 ) v ol2 6ma sink current 0 0.6 v i/o capacitance c i/o 10 pf i/o pullup resistor value r i/o 3.5 5 7.0 k ? 3v (note 2) 160 300 standby current i stby 5v (note 2) 195 350 ? *this voltage must not exceed 6.0v.
DS3930 hex nonvolatile potentiometer with i/o and memory _____________________________________________________________________ 3 ac electrical characteristics (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise specified.) parameter symbol conditions min typ max units fast mode 0 400 scl clock frequency (note 3) f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start condition (note 3) t buf standard mode 4.7 ? fast mode 0.6 hold time (repeated) start condition (notes 3 and 4) t hd:sta standard mode 4.0 ? fast mode 1.3 low period of scl clock (note 3) t low standard mode 4.7 ? fast mode 0.6 high period of scl clock (note 3) t high standard mode 4.0 ? analog resistor characteristics (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise specified.) parameter symbol conditions min typ max units end-to-end resistance t a = +25? (three 50k ? pots in parallel) 13.2 16.5 19.8 k ? wiper resistance r w 400 1000 ? factory default wiper setting ff hex factory default i/o setting 0f hex pot-to-pot matching -1 +1 lsb differential linearity -0.5 +0.5 lsb integral linearity -1 +1 lsb end-to-end temperature coefficient 3 potentiometers in parallel -250 0 +250 ppm/? ratiometric temperature coefficient 2 ppm/?
DS3930 hex nonvolatile potentiometer with i/o and memory 4 ______________________________________________________________________ note 1: all voltages are referenced to ground. note 2: i stby specified for v cc equal 3.0v and 5.0v, sda = scl = v cc , and i/o 0 = i/o 1 = i/o 2 = i/o 3 = a0 = a1 = a2 = gnd. note 3: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns +250ns = 1250ns before the scl line is released. note 4: after this period, the first clock pulse is generated. note 5: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 6: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl sig- nal) in order to bridge the undefined region of the falling edge of scl. note 7: c b ?otal capacitance of one bus line in picofarads, timing referenced to 0.9v cc and 0.1v cc. note 8: eeprom write begins after a stop condition occurs. ac electrical characteristics (continued) (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise specified.) parameter symbol conditions min typ max units fast mode 0 0.9 data hold time (notes 3, 5, 7) t hd:dat standard mode 0 0.9 ? fast mode 100 data setup time (note 3) t su:dat standard mode 250 ns fast mode 0.6 start setup time (note 3) t su:sta standard mode 4.7 ? fast mode 20 + 0.1c b 300 rise time of both sda and scl signals (note 7) t r standard mode 20 + 0.1c b 1000 ns fast mode 20 + 0.1c b 300 fall time of both sda and scl signals (note 7) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 ? capacitive load for each bus c b (note 7) 400 pf eeprom write time t w (note 8) 5 20 ms eeprom characteristics (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise specified.) parameter symbol conditions min typ max units writes +70?c 50,000
DS3930 hex nonvolatile potentiometer with i/o and memory _____________________________________________________________________ 5 voltage divider % change from +25 c vs. temperature DS3930 toc06 temperature ( c) resistance % change (from +25 c) 80 60 -20 0 20 40 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 -40 100 hi = v cc lo 0-5 = gnd position 127 end-to-end resistance % change from +25 c vs. temperature DS3930 toc05 temperature ( c) resistance % change (from +25 c) 80 60 20 40 0 -20 -0.80 -0.60 -0.40 -0.20 0 0.20 0.40 0.60 0.80 1.00 -1.00 -40 100 3 pots in parallel measured from hi 0-2 to lo 0-5 wiper voltage vs. power-up voltage DS3930 toc04 power-up voltage (v) wiper voltage (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 0 0 5.0 hi = 5v, lo = gnd position 127 eeprom recall follows v cc changes to programmed value once eeprom is recalled active supply current vs. scl frequency DS3930 toc03 scl frequency (khz) supply current ( a) 300 200 100 260 320 380 440 500 560 620 680 740 200 0 400 v cc = 5v v cc = 3v sda = v cc wiper voltage vs. wiper setting DS3930 toc02 setting (dec) voltage (v) 250 200 150 100 50 1 2 3 4 5 6 0 0 300 hi = 5v lo = gnd supply current vs. temperature DS3930 toc01 temperature ( c) supply current ( a) 80 60 40 20 0 -20 140 160 180 200 220 120 -40 100 v cc = 5v v cc = 3v sda = scl = 5v t ypical operating characteristics (v cc = 5.0v; t a = +25?, unless otherwise specified.) all pots dnl (lsb) DS3930 toc08 position (dec) dnl (lsb) 225 200 150 175 50 75 100 125 25 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 250 pots 1, 3, 5 inl (lsb) DS3930 toc09 position (dec) inl (lsb) 225 200 150 175 50 75 100 125 25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 250 pots 0, 2, 4, inl (lsb) DS3930 toc07 position (dec) inl (lsb) 225 200 150 175 50 75 100 125 25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 250
pin description pin name function 1a 0 address input. the address input pins determine the 2-wire address of the device. 2a 1 address input 3a 2 address input 4 sda 2-wire serial data i/o. this pin is for serial data transfer to and from the device. 5 scl 2-wire serial clock input. the serial clock input is used to clock data into and out of the device. 6 i/o 0 general-purpose nv i/o pin 7 i/o 1 general-purpose nv i/o pin 8 i/o 2 general-purpose nv i/o pin 9v cc supply voltage 10 gnd ground 11 i/o 3 general-purpose nv i/o pin 12 w 5 wiper terminal of potentiometer 5 13 w 4 wiper terminal of potentiometer 4 14 w 3 wiper terminal of potentiometer 3 15 hi 3-5 high-end terminal of potentiometers 3 to 5. this is the common high-side terminal of potentiometers 3, 4, and 5. 16 lo 0-5 low-end terminal of the potentiometers. this is the common low-side terminal of all six potentiometers. 17 w 2 wiper terminal of potentiometer 2 18 w 1 wiper terminal of potentiometer 1 19 w 0 wiper terminal of potentiometer 0 20 hi 0-2 high-end terminal of potentiometers 0 to 2. this is the common high-side terminal of potentiometers 0, 1, and 2. DS3930 hex nonvolatile potentiometer with i/o and memory 6 ______________________________________________________________________
detailed description the DS3930 contains six nv potentiometers with 64 bytes of nv user memory (eeprom), and four pro- grammable nv i/o pins. figure 1 is a functional dia- gram of the DS3930. potentiometers the six potentiometers share a common low side and are separated into two groups of three potentiometers, each group sharing a common high side. the six 256- position potentiometers are controllable using six 8-bit eeprom registers through the 2-wire interface. DS3930 hex nonvolatile potentiometer with i/o and memory _____________________________________________________________________ 7 2-wire interface v cc a0 sda scl a1 a2 gnd pot0 50k ? 50k ? 50k ? 50k ? 50k ? 50k ? pot1 pot2 pot3 pot4 pot5 w 0 w 1 w 2 w 3 w 4 w 5 hi 0-2 lo 0-5 hi 3-5 i/o 0 i/o 1 i/o 2 i/o 3 i/o cell x 4 64 bytes of eeprom reserved pot0 control i/o control i/o state reserved ffh f8h f7h f6h f5h pot1 control pot2 control pot3 control pot4 control pot5 control f1h f2h f3h f4h efh f0h 00h 3fh 40h 8 8 8 8 8 8 8 4 eeprom DS3930 figure 1. DS3930 functional diagram
DS3930 hex nonvolatile potentiometer with i/o and memory 8 ______________________________________________________________________ i/o signals the i/o pins can be used as general-purpose digital i/o signals. the i/o pins have cmos outputs with an internal pullup resistor (see figure 2). the i/o pins are configured with the i/o control register (f6h) and moni- tored with the i/o state register (f7h). the i/o control register controls the state of the internal pullup resistor (r i/o ) with bits 7 to 4 and the i/o pin setting with bits 3 to 0 (see table 1). the read-only values of the i/o state register contains the values of the i/o pin setting bits of the i/o control register unless the i/o output is tri-stat- ed. when the i/o is tri-stated the i/o state register will read high or low depending on the external source on the i/o pin. since the i/o pins are controlled by eep- rom, the number of writes is limited. memory the memory map is shown in table 2. table 2. memory map address bit default (hex) function 00h to 3fh ff 64 bytes of general-purpose eeprom 40h to efh ff reserved f0h ff controls potentiometer 0 f1h ff controls potentiometer 1 f2h ff controls potentiometer 2 f3h ff controls potentiometer 3 f4h ff controls potentiometer 4 f5h ff controls potentiometer 5 f6h 0f i/o control bit 7 set to 0 to enable i/o 3 pullup, set to 1 to disable pullup bit 6 set to 0 to enable i/o 2 pullup, set to 1 to disable pullup bit 5 set to 0 to enable i/o 1 pullup, set to 1 to disable pullup bit 4 set to 0 to enable i/o 0 pullup, set to 1 to disable pullup bit 3 sets i/o 3 to 0 or 1 bit 2 sets i/o 2 to 0 or 1 bit 1 sets i/o 1 to 0 or 1 bit 0 sets i/o 0 to 0 or 1 f7h 0x i/o state bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 contains state of i/o 3 pin (read only) bit 2 contains state of i/o 2 pin (read only) bit 1 contains state of i/o 1 pin (read only) bit 0 contains state of i/o 0 pin (read only) f8h to ffh ff reserved pullup ctrl (i/o control register) (bits 7 to 4) i/o pin setting (i/o control register) (bits 3 to 0) i/o pin output 00 0 01 1 10 0 11 pullup disabled (hi-z) table 1. i/o pin truth table
DS3930 hex nonvolatile potentiometer with i/o and memory _____________________________________________________________________ 9 2-wire serial port operation the 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a trans- mitter, and a device receiving data as a receiver. the device that controls the message is called a ?aster. the devices that are controlled by the master are ?laves.?the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop con- ditions. the DS3930 operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines, sda and scl. the following i/o terminals control the 2-wire serial port: sda, scl, and a0. timing diagrams for the 2-wire serial port can be found in figures 3 and 5. timing information for the 2- wire serial port is provided in the ac electrical characteristics table for 2-wire serial communications. the following bus protocol has been defined: data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line can be changed during the low period of the clock signal. there is one clock pulse per bit of data. figures 3 and 5 detail how data transfer is accomplished on the 2-wire bus. depending upon the state of the r/w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 3. 2-wire data transfer protocol pullup ctrl i/o pin setting r i/o v cc esd i/o input figure 2. i/o cell
DS3930 hex nonvolatile potentiometer with i/o and memory 10 _____________________________________________________________________ terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications, a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the DS3930 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. the master device must generate an extra clock pulse that is associated with this acknowl- edge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the com- mand/control byte) to the slave. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the mas- ter returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge can be returned. the master device generates all serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. the DS3930 can operate in the following three modes: 1) slave receiver mode: serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is trans- mitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the DS3930 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. 3) slave address: this is the first byte received fol- lowing the start condition from the master device. the slave address consists of a 4-bit control code. for the DS3930, this is set as 1010 binary for read/write operations. the next bits of the slave address are the device address (a2?0). the last bit of the slave address (r/w) defines the operation to be performed. when set to a ?,?a read operation is selected, and when set to a ?,?a write operation is selected (see figure 4). following the start condition, the DS3930 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1010 device identifier, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. msb device identifier device address read/write bit 1 010a2 a1 a0 r/w lsb figure 4. slave address
DS3930 hex nonvolatile potentiometer with i/o and memory ____________________________________________________________________ 11 applications information power supply decoupling to achieve the best results when using the DS3930, decouple the power supply with a 0.1? high-quality, ceramic, surface-mount capacitor. surface-mount com- ponents minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. the capacitor should be placed as close as possible to the v cc and gnd pins. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 5. 2-wire ac characteristics slave ack 10 0 1 r/w a0* a1* slave ack a2* msb lsb device identifier device address read/ write msb lsb register address slave ack msb lsb b7 b6 b5 b4 b3 b2 b1 b0 slave ack stop *the address determined by a0, a1, and a2 must match the address set by the address pins. d ata typical 2-wire write transaction example 2-wire transactions (when a0, a1, and a2 are zero) a) single-byte write -write to pot 0 register b) single-byte read -read from pot 0 register d) multiple byte write -2 byte write to eeprom e) multiple byte read -2 byte read from eeprom start start start start start a0h a0h a0h a0h slave ack slave ack slave ack slave ack f0h f0h 00h 00h slave ack slave ack slave ack slave ack d ata slave ack stop pot setting 10100000 10100000 10100000 10100000 10100001 repeated start slave ack master ack d ata master nack stop d ata a1h b7 b6 b5 b4 b3 b2 b1 b0 11110000 c) single-byte write -set i/o 0 pin to a "1" start a0h slave ack f6h slave ack d ata slave ack stop xxx0xxx1 10100000 11110110 11110000 00000000 00000000 repeated start d ata pot setting master nack stop slave ack 10100001 a1h stop slave ack d ata slave ack d ata figure 6. example 2-wire transactions
DS3930 hex nonvolatile potentiometer with i/o and memory maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. wiper resistance one difference between digital potentiometers and mechanical potentiometers is the wiper resistance. the wiper resistance (r w ) is a result of the interconnecting materials on the ic between the internal resistive ele- ments and the wiper pin. this can be modeled by using an ideal potentiometer, with a resistance of r w con- nected between the ideal wiper and wiper terminal of the digital potentiometer. chip information transistor count: 27,000 substrate connected to ground. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .

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